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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. october 2008 rev 4 1/17 1 nand32gw3d4a 32-gbit (2 x 16 gbits), two chip enable, 4224-byte page, multilevel cell, 3 v supply, mu ltiplane, nand flash memory features high density multilevel cell (mlc) flash memory ? 32 gbits of memory array ? 1 gbit of spare area ? cost-effective solutions for mass storage applications nand interface ? x8 bus width ? multiplexed address/data supply voltage: v dd = 2.7 to 3.6 v page size: (4096 + 128 spare) bytes block size: (512k + 16k spare) bytes multiplane architecture ? array split into two independent planes ? all operations can be performed on both planes simultaneously memory cell array: ? (4 k + 128) bytes x 128 pages x 8192 blocks (2 dice x16 gbits, 2 chip enable) page read/program ? random access: 60 s (max) ? sequential access: 25 ns (min) ? page program operation time: 800 s (typ) multipage program time (2 pages): 800 s (typ) copy-back program ? fast page copy fast block erase ? block erase time: 2.5 ms (typ) multiblock erase time (2 blocks): 2.5 ms (typ) status register electronic signature serial number option chip enable ?don?t care? data protection ? hardware program/erase locked during power transitions development tools ? error correction code models ? bad block management and wear leveling algorithm ? hw simulation models data integrity ? 10,000 program/erase cycles (with ecc) ? 10 years data retention ecopack ? packages available tsop48 12 x 20 mm (n) www.numonyx.com
nand32gw3d4a 2/17 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 bad blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 chip enable (e 1 , e 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 read enable (r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.6 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 ready/busy (rb 1 , rb 2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.10 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
nand32gw3d4a 3/17 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. electronic signature code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 6. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 8. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 14 table 9. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
nand32gw3d4a 4/17 list of figures figure 1. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tsop48 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 14
nand32gw3d4a description 5/17 1 description the nand32gw3d4a is a multilevel cell (mlc ) device from the nand flash 4224-byte page family of non-volatile flash memories. the nand32gw3d4a has a density of 32 gbits and combines two 16-gbit dice in a stacked device. each dice has its own chip enable and ready/busy pin so that it can be driven independently using the relative chip enable pin. moreover, each dice has its own maximum number of bad blocks and its own electronic signature code (see ta b l e 2 ). the device operates from a 3 v power supply. this document must be read in conjunct ion with the nandxxgw3d2 a datasheet, which fully details all the specifications required to operate the 16-gbit flash memory component. the device is available in tsop48 (12 20 mm) package and is shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. refer to the list of available part numbers and to table 9: ordering information scheme for information on how to order these options. table 1. device summary part number density bus width page size block size memory array operating voltage (v dd ) timings package random access time (max) sequential access time (min) page program (typ) block erase (typ) nand3 2gw3d 4a 32 gbits x8 4096+ 128 bytes 512k + 16k bytes 128 pages x 8192 blocks 2.7 to 3.6 v 60 s 25 ns 800 s 2.5 ms tsop48 table 2. electronic signature code device organization v dd 1st 2nd 3rd 4th 5th 16 gbits x8 3 v 20h d5h 14h b6h 44h
description nand32gw3d4a 6/17 figure 1. functional block diagram ai11031b e 2 i/o0-i/o7 v dd al cl r wp w 16-gbit flash memory 16-gbit flash memory e 1 rb 1 v ss rb 2
nand32gw3d4a description 7/17 figure 2. logic diagram table 3. signal names signal function direction i/o0 - i/o7 data inpu t/outputs input/output cl command latch enable input al address latch enable input e 1 , e 2 chip enable input r read enable input w write enable input wp write protect input rb 1 , rb 2 ready/busy (open drain output) output v dd power supply power supply v ss ground ground nc no connection ? du do not use ? ai13632b i/o0 - i/o7 x8 v dd nand flash w v ss wp al cl e 1 r rb 1 e 2 rb 2
description nand32gw3d4a 8/17 figure 3. tsop48 connections i/o3 i/o2 i/o6 r rb1 rb2 i/o4 i/o7 ai13169 nand flash 12 1 13 24 25 36 37 48 e1 i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al e2 nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc
nand32gw3d4a memory array organization 9/17 2 memory array organization the memory array is split into two dice. each dice is comprised of nand structures where 32 cells are connected in series. it is organized into blocks where each block contains 128 pages. the array is split into two areas, the main area and the spare area. the main area of the array stores data, whereas the spare area typically stores software flags or bad block identification. the pages are split into a 4096-byte main area and a spare area of 128 bytes. 2.1 bad blocks the nand32gw3d4a device may contain bad bl ocks, where the reliab ility of blocks that contain one or more invalid bits is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to the bad block management section of the nandxxgw3d2a datasheet for more details). table 4: valid blocks shows the minimum number of valid blocks. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. each dice can have the same maximum number of bad blocks. these blocks need to be managed using bad blocks management and block replacement (refer to the software algorithms section of the nandxxgw3d2a datasheet). 2.2 parallel operation the nand32gw3d4a is composed of two dice, each one driven by its chip enable pin (e 1 and e 2 , respectively). it is possible to drive the two dice in parallel, thus increasing the throughput in mbyte/s. when one of the two dice is in a busy state, every operation can be issued on the other available dice. table 4. valid blocks density of device minimum maximum 32 gbits 7992 8192
signal descriptions nand32gw3d4a 10/17 3 signal descriptions see figure 1: functional block diagram , and table 3: signal names for a brief overview of the signals connected to this device. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used to input the selected address, output the data during a read operation, or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.3 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.4 chip enable (e 1 , e 2 ) the chip enable input activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains selected and does not go into standby mode. 3.5 read enable (r ) the read enable pin, r , controls the sequential data output during read operations. data is valid t rlqv after the fallin g edge of r . the falling edge of r also increments the internal column address co unter by one. 3.6 write enable (w ) the write enable input, w , controls writing to the command interface, input address, and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time.
nand32gw3d4a signal descriptions 11/17 3.7 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.8 ready/busy (rb 1 , rb 2 ) the ready/busy output, rb 1 and rb 2 , is an open-drain output that can identify if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes, ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low indi cates that one, or more, of the memories is busy. during power-up and power-down a minimum recovery time of 10 s is required before the command interface is ready to accept a command. during this period the ready/busy signal is low, v ol . refer to section 6: package mechanical for details on how to calculate the value of the pull- up resistor. 3.9 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). an internal voltage detector disables all functions whenever v dd is below v lko to protect the device from any involuntary program/erase during power transitions. each device in a system should have v dd decoupled with a 0.1 f capacitor. the pcb track widths should be sufficient to carry the required program and erase currents. 3.10 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
maximum ratings nand32gw3d4a 12/17 4 maximum ratings stressing the device above the ratings listed in table 5: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. table 5. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) 1. minimum voltage may undershoot to ?2 v for less t han 20 ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2 v for less than 20 ns dur ing transitions on i/o pins. input or output voltage ? 0.6 4.6 v v dd supply voltage ? 0.6 4.6 v
nand32gw3d4a dc and ac parameters 13/17 5 dc and ac parameters this section summarizes the operating and measurement conditions as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristics tables are derived from tests performed under the measurement conditions summarized in table 6: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. table 6. operating and ac measurement conditions parameter min max units supply voltage (v dd )2.7 3.6v ambient temperature (t a ) ?40 85 c load capacitance (c l ) (1 ttl gate and c l )50pf input pulses voltages 0 v dd v input and output timing ref. voltages 1.5 v output circuit resistor r ref 8.35 k ? input rise and fall times 5 ns table 7. capacitance (1) 1. t a = 25 c, f = 1 mhz. c in and c i/o are not 100% tested. symbol parameter test condition typ max unit c in input capacitance v in = 0 v 10 pf c i/o input/output capacitance v il = 0 v 10 pf
package mechanical nand32gw3d4a 14/17 6 package mechanical to meet environmental requirements, numonyx offers these devices in ecopack? packages. ecopack? packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 4. tsop48 - 48 lead plastic thin sm all outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 8. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a1.200.047 a1 0.10 0.05 0.15 0.004 0.002 0.006 a2 1.00 0.95 1.05 0.039 0.037 0.041 b 0.22 0.17 0.27 0.009 0.007 0.011 c 0.10 0.21 0.004 0.008 cp 0.08 0.003 d1 12.00 11.90 12.10 0.472 0.468 0.476 e 20.00 19.80 20.20 0.787 0.779 0.795 e1 18.40 18.30 18.50 0.724 0.720 0.728 e 0.50 ? ? 0.020 ? l 0.60 0.50 0.70 0.024 0.020 0.028 l1 0.80 0.031 a 305305
nand32gw3d4a ordering information 15/17 7 ordering information note: devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest numonyx sales office. table 9. ordering information scheme example: nand32g w 3 d 4 a n 6 e device type nand flash memory density 32g = 32 gbits operating voltage w = v dd = 2.7 to 3.6 v bus width 3 = x8 family identifier d = 4 kbyte-page mlc device options 4 = chip enable ?don't care? enabled with 2 chip enable and 2 ready/busy signals product version a = first version package n = tsop48 12 x 20 mm temperature range 6 = ? 40 to 85 c option e = ecopack? package, standard packing f = ecopack? package, tape and reel packing
revision hist ory nand32gw3d4a 16/17 8 revision history table 10. document revision history date revision changes 05-jun-2008 1 initial release. 09-jul-2008 2 modified: density of spare area ? on page 1 , figure 1: functional block diagram , and section 3.9: vdd supply voltage . 08-aug-2008 3 modified the reference to the 16-gbit flash memory component datasheet (from nand16gw3d2a to nandxxgw3d2a). 24-oct-2008 4 added table 2: electronic signature code .
nand32gw3d4a 17/17 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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